FIG. 1 shows a portion of a conventional floating gate memory device 10. Floating gate memory devices such as device 10 may be programmed using hot electron injection and erased using Fowler-Nordheim tunneling as is well-known and described in detail in U.S. Pat. Nos. 5,029,130 and 5,289,411. The device 10 includes a memory array 12 of floating gate memory cells 14. The memory array 12 includes a plurality of wordlines WL(j), j=1, 2, . . . J and a plurality of bitlines BL(k), k=1, 2, . . . K. A floating gate memory cell 14 located at the intersection of each WL(j) and bitline BL(k) is used to store a single bit of data. The device 10 includes an address input buffer 16 which receives an N-bit input address ADDR(0:N) designating a particular wordline WL(j) of cells 14 in the array 12. The address buffer 16 supplies portions of the input address ADDR(0:N) to an X or row pre-decoder 18. The X pre-decoder 18 supplies partially-decoded wordline address signals to a worldwide decoder 20 which selects the particular wordline WL(j) corresponding to the input address ADDR(0:N). The address buffer 16 also supplies a portion of the input address to a Y or column pre-decoder 22, which in turn supplies partially-decoded bitline address signals to a bitline decoder 24.
The device 10 in this example is configured as an 8-bit device and bitline decoder 24 therefore selects eight bitlines BL(k) corresponding to a group of eight memory cells 12 on the selected wordline WL(j), and supplies the data programmed in the selected cells to one input of a multiple sensing amplifier 26 via data lines DL(0:7). The multiple sensing amplifier 26 includes eight sensing amplifiers, each of which compare the data signal on one of the lines DL(0:7) to a reference SENREF. The multiple sensing amplifier 26 thus senses and amplifies the retrieved data on data lines DL(0:7) and supplies the resulting signals to an output buffer 28. The output buffer 28 supplies the retrieved data to output pins DQ(0:7) when enabled by an output enable (OE) signal supplied by a control logic circuit 30. The control logic circuit 30 receives complements of the OE signal, a chip enable (CE) signal and a write enable (WE) signal, and controls the operation of address input buffer 16 as well as other elements of the device 10. The device 10 may be configured as a 16-bit device, 32-bit device and so on by suitable alteration of the number of bitlines in a particular selected group of bitlines BL(k), the number of sensing amplifiers in multiple sensing amplifier 26, and the number of lines DL, DQ and the like.
Data may be programmed into the cells 14 of a selected word line WL(j) of array 12 in the following manner. The wordline decoder 20 supplies a threshold potential typically less than +5 volts to the selected wordline WL(j) and thereby to the gates of the cells 14 coupled to that wordline. A voltage of approximately +12 volts is supplied from a high voltage (HV) decoder (not shown) to the source of each of the cells 14 in the selected wordline via a corresponding N+ source line SL(j). A given cell 14 in the selected wordline is then programmed to a particular logic value by bringing the corresponding bitline BL(k) and thereby the drain of the given cell 14 to either 0 volts or +5 volts depending on the logic value to be programmed. Hot electrons from the source of the given cell 14 can thereby be injected into and stored on the floating gate of the cell.
Data may be read back from the cells 14 of a selected wordline WL(j) by bringing the sources of the cells to ground potential via source line SL(j), the drains of the cells to a read voltage on the order of +2 volts via corresponding bitlines BL(k), and the gates of the cells to about +5 volts via wordline WL(j). This will generate for each cell a signal indicative of the stored charge in that cell. These signals are amplified by sense amplifier 26 and supplied to output buffer 28 in the manner previously described.
Data may be erased from the cells 14 of a selected wordline WL(j) by bringing the source of the cells to ground potential via source line SL(j), the drains of the cells to ground potential via corresponding bitlines BL(k), and the gates of the cells to a potential of about +15 volts via the wordline WL(j). The high voltage potential on the gate of the floating gate cells 14 causes the charge stored on the floating gate to be removed by the mechanism of Fowler-Nordheim tunneling.
The above-described programming and erasing operations generally involve applying relatively high DC voltages to the cells 12 for periods of time on the order of milliseconds or microseconds. However, the contents of the memory cells 14 may also be unintentionally altered if lower DC voltages are applied to the cells for much longer periods of time. For example, the above-described read operation involves applying a voltage on the order of +5 volts to the gates of the memory cells 14 in a selected wordline WL(j). If the memory device 10 is placed in an active read mode in which +5 volts is applied to the gates of the cells 14 but no wordline or bitline addresses change for a relatively long period of time, the cells 14 may gradually gain or lose charge such that the stored logic values may be unintentionally altered. This unintentional alteration of stored charge under DC stress over relatively long periods of time is referred to as "read disturbance."
FIG. 2 is a timing diagram illustrating the read disturbance problem in greater detail. Several of the signals shown in the device 10 of FIG. 1 are illustrated over three time periods A, B and C. During period A, the device 10 is inactive as indicated by the logic high level of the complemented CE signal applied to control logic circuit 30. The input address ADDR(0:N) is therefore ignored and the wordline (WL) signal and bitline (BL) signal are maintained at logic low levels such that all wordlines and bitlines are deselected.
During period B, the complemented CE signal goes low, and the device 10 is placed in an active read mode. The input address specifies a particular selected wordline WL(m) and a group of selected bitlines designated BL(n). In accordance with the above-described read operation, the selected wordline WL(m) is brought to a voltage of about +5 volts and the selected group of multiple bitlines BL(n) are brought to a read voltage on the order of +2 volts as shown in FIG. 2. The data from the cells designated by the intersection of wordline WL(m) and bitlines BL(n) is then read out in the manner previously described.
During period C, the complemented CE signal remains low and device 10 remains in an active read mode. The input address ADDR(0:N) in period C specifies a different wordline WL(j) and set of bitlines BL(k), such that the selected wordline WL(j) is brought to a voltage of about +5 volts and the selected bitlines BL(k) are brought to a read voltage on the order of +2 volts as shown. However, the active read mode of period C is a "DC idle" read mode in which the input address ADDR(0:N) does not change for an extended period of time. This places multiple cells on selected wordline WL(j) under a long-term DC stress on the order of +5 volts, places multiple cells on selected bitlines BL(k) under a long-term DC stress on the order of +2 volts, and places selected cells at the intersection of WL(j) and BL(k) under both +5 volt and +2 volt stresses.
As noted above, such long-term DC voltage stresses can result in the unintentional alteration of stored charge in the stressed cells, leading to the loss of programmed data and therefore device malfunction. Conventional memory devices such as device 10 of FIG. 1 provide no sufficiently effective mechanism for reducing or otherwise alleviating these read disturbance effects.
It is therefore an object of the present invention to provide an improved memory device in which read disturbance effects may be substantially eliminated without unduly increasing the die size or power consumption of the device.